// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  peri_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  Huawei
// Version       :  1.0
// Date          :  2017/11/13
// Description   :  The description of Hi MINI project
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/05/16 10:46:15 Create file
// ******************************************************************************

#ifndef __PERI_REG_OFFSET_FIELD_H__
#define __PERI_REG_OFFSET_FIELD_H__

#define PERI_CER_REG_LEN    40
#define PERI_CER_REG_OFFSET 0

#define PERI_AXI_COMM_LEN    40
#define PERI_AXI_COMM_OFFSET 0

#define PERI_SMB_LEN    40
#define PERI_SMB_OFFSET 0

#define PERI_SFC_REG_LEN    40
#define PERI_SFC_REG_OFFSET 0

#define PERI_SFC_MEM_LEN    40
#define PERI_SFC_MEM_OFFSET 0

#define PERI_CFGBUS_A55_LEN    40
#define PERI_CFGBUS_A55_OFFSET 0

#define PERI_IPC_REG_LEN    40
#define PERI_IPC_REG_OFFSET 0

#define PERI_SDMAM_REG_LEN    40
#define PERI_SDMAM_REG_OFFSET 0

#define PERI_DISP_REG_LEN    40
#define PERI_DISP_REG_OFFSET 0

#define PERI_SCHE_REG_LEN    40
#define PERI_SCHE_REG_OFFSET 0

#define PERI_FTE_REG_LEN    40
#define PERI_FTE_REG_OFFSET 0

#define PERI_SMMU_REG3_LEN    40
#define PERI_SMMU_REG3_OFFSET 0

#define PERI_SMMU_REG2_LEN    40
#define PERI_SMMU_REG2_OFFSET 0

#define PERI_SMMU_REG1_LEN    40
#define PERI_SMMU_REG1_OFFSET 0

#define PERI_SMMU_REG0_LEN    40
#define PERI_SMMU_REG0_OFFSET 0

#define PERI_CFGBUS_LEN    40
#define PERI_CFGBUS_OFFSET 0

#define PERI_EMMC_REG_LEN    40
#define PERI_EMMC_REG_OFFSET 0

#define PERI_UART0_REG_LEN    40
#define PERI_UART0_REG_OFFSET 0

#define PERI_GPIO1_REG_LEN    40
#define PERI_GPIO1_REG_OFFSET 0

#define PERI_IOMUX_REG_LEN    40
#define PERI_IOMUX_REG_OFFSET 0

#define PERI_TRNG_REG_LEN    40
#define PERI_TRNG_REG_OFFSET 0

#define PERI_EXMBIST1_REG_LEN    40
#define PERI_EXMBIST1_REG_OFFSET 0

#define PERI_DDRC7_REG1_LEN    40
#define PERI_DDRC7_REG1_OFFSET 0

#define PERI_DDRC7_REG0_LEN    40
#define PERI_DDRC7_REG0_OFFSET 0

#define PERI_DDRC6_REG1_LEN    40
#define PERI_DDRC6_REG1_OFFSET 0

#define PERI_DDRC6_REG0_LEN    40
#define PERI_DDRC6_REG0_OFFSET 0

#define PERI_DDRC5_REG1_LEN    40
#define PERI_DDRC5_REG1_OFFSET 0

#define PERI_DDRC5_REG0_LEN    40
#define PERI_DDRC5_REG0_OFFSET 0

#define PERI_DDRC4_REG1_LEN    40
#define PERI_DDRC4_REG1_OFFSET 0

#define PERI_DDRC4_REG0_LEN    40
#define PERI_DDRC4_REG0_OFFSET 0

#define PERI_TIMER29_REG_LEN    40
#define PERI_TIMER29_REG_OFFSET 0

#define PERI_TIMER28_REG_LEN    40
#define PERI_TIMER28_REG_OFFSET 0

#define PERI_TIMER27_REG_LEN    40
#define PERI_TIMER27_REG_OFFSET 0

#define PERI_TIMER26_REG_LEN    40
#define PERI_TIMER26_REG_OFFSET 0

#define PERI_TIMER25_REG_LEN    40
#define PERI_TIMER25_REG_OFFSET 0

#define PERI_TIMER24_REG_LEN    40
#define PERI_TIMER24_REG_OFFSET 0

#define PERI_TIMER23_REG_LEN    40
#define PERI_TIMER23_REG_OFFSET 0

#define PERI_TIMER22_REG_LEN    40
#define PERI_TIMER22_REG_OFFSET 0

#define PERI_TIMER21_REG_LEN    40
#define PERI_TIMER21_REG_OFFSET 0

#define PERI_TIMER20_REG_LEN    40
#define PERI_TIMER20_REG_OFFSET 0

#define PERI_TIMER19_REG_LEN    40
#define PERI_TIMER19_REG_OFFSET 0

#define PERI_TIMER18_REG_LEN    40
#define PERI_TIMER18_REG_OFFSET 0

#define PERI_TIMER17_REG_LEN    40
#define PERI_TIMER17_REG_OFFSET 0

#define PERI_TIMER16_REG_LEN    40
#define PERI_TIMER16_REG_OFFSET 0

#define PERI_TIMER15_REG_LEN    40
#define PERI_TIMER15_REG_OFFSET 0

#define PERI_TIMER14_REG_LEN    40
#define PERI_TIMER14_REG_OFFSET 0

#define PERI_TIMER13_REG_LEN    40
#define PERI_TIMER13_REG_OFFSET 0

#define PERI_TIMER12_REG_LEN    40
#define PERI_TIMER12_REG_OFFSET 0

#define PERI_TIMER11_REG_LEN    40
#define PERI_TIMER11_REG_OFFSET 0

#define PERI_TIMER10_REG_LEN    40
#define PERI_TIMER10_REG_OFFSET 0

#define PERI_TIMER9_REG_LEN    40
#define PERI_TIMER9_REG_OFFSET 0

#define PERI_TIMER8_REG_LEN    40
#define PERI_TIMER8_REG_OFFSET 0

#define PERI_TIMER7_REG_LEN    40
#define PERI_TIMER7_REG_OFFSET 0

#define PERI_TIMER6_REG_LEN    40
#define PERI_TIMER6_REG_OFFSET 0

#define PERI_TIMER5_REG_LEN    40
#define PERI_TIMER5_REG_OFFSET 0

#define PERI_TIMER4_REG_LEN    40
#define PERI_TIMER4_REG_OFFSET 0

#define PERI_TIMER3_REG_LEN    40
#define PERI_TIMER3_REG_OFFSET 0

#define PERI_TIMER2_REG_LEN    40
#define PERI_TIMER2_REG_OFFSET 0

#define PERI_TIMER1_REG_LEN    40
#define PERI_TIMER1_REG_OFFSET 0

#define PERI_TIMER0_REG_LEN    40
#define PERI_TIMER0_REG_OFFSET 0

#define PERI_SECURE WDG0_REG1_LEN    40
#define PERI_SECURE WDG0_REG1_OFFSET 0

#define PERI_SECURE WDG0_REG0_LEN    40
#define PERI_SECURE WDG0_REG0_OFFSET 0

#define PERI_WDG9_REG1_LEN    40
#define PERI_WDG9_REG1_OFFSET 0

#define PERI_WDG9_REG0_LEN    40
#define PERI_WDG9_REG0_OFFSET 0

#define PERI_WDG8_REG1_LEN    40
#define PERI_WDG8_REG1_OFFSET 0

#define PERI_WDG8_REG0_LEN    40
#define PERI_WDG8_REG0_OFFSET 0

#define PERI_WDG7_REG1_LEN    40
#define PERI_WDG7_REG1_OFFSET 0

#define PERI_WDG7_REG0_LEN    40
#define PERI_WDG7_REG0_OFFSET 0

#define PERI_WDG6_REG1_LEN    40
#define PERI_WDG6_REG1_OFFSET 0

#define PERI_WDG6_REG0_LEN    40
#define PERI_WDG6_REG0_OFFSET 0

#define PERI_WDG5_REG1_LEN    40
#define PERI_WDG5_REG1_OFFSET 0

#define PERI_WDG5_REG0_LEN    40
#define PERI_WDG5_REG0_OFFSET 0

#define PERI_WDG4_REG1_LEN    40
#define PERI_WDG4_REG1_OFFSET 0

#define PERI_WDG4_REG0_LEN    40
#define PERI_WDG4_REG0_OFFSET 0

#define PERI_WDG3_REG1_LEN    40
#define PERI_WDG3_REG1_OFFSET 0

#define PERI_WDG3_REG0_LEN    40
#define PERI_WDG3_REG0_OFFSET 0

#define PERI_WDG2_REG1_LEN    40
#define PERI_WDG2_REG1_OFFSET 0

#define PERI_WDG2_REG0_LEN    40
#define PERI_WDG2_REG0_OFFSET 0

#define PERI_WDG1_REG1_LEN    40
#define PERI_WDG1_REG1_OFFSET 0

#define PERI_WDG1_REG0_LEN    40
#define PERI_WDG1_REG0_OFFSET 0

#define PERI_WDG0_REG1_LEN    40
#define PERI_WDG0_REG1_OFFSET 0

#define PERI_WDG0_REG0_LEN    40
#define PERI_WDG0_REG0_OFFSET 0

#define PERI_TZPC_REG_LEN    40
#define PERI_TZPC_REG_OFFSET 0

#define PERI_SUBCTRL_REG_LEN    40
#define PERI_SUBCTRL_REG_OFFSET 0

#define PERI_ITS_LEN    40
#define PERI_ITS_OFFSET 0

#define PERI_GIC0_LEN    40
#define PERI_GIC0_OFFSET 0

#define PERI_GIC1_LEN    40
#define PERI_GIC1_OFFSET 0

#endif // __PERI_REG_OFFSET_FIELD_H__
